Digital communication of information from a source to a receiver may be done source synchronously. Source synchronous communication involves a clock signal from the source (“forwarded clock signal”) being sent in parallel with other information from the source. Such other information may include data or control information, where control information may include address information.
There are different types of source synchronous communication, which depends on the application. For example, for source synchronous communication with synchronous memory, frequency of a source clock signal is known by a receiving device, and sent data tends to be relatively closely associated with the source clock signal. However, for example in source synchronous communication in networking or telecommunication, frequency of a source clock signal may not be known by the receiving device. Furthermore, due to differences in signal propagation delays, there may be skew between information communicated in parallel with the source clock signal. Accordingly, received serial information converted to parallel information may be out of order. The operation or operations to put such digital data back into order or otherwise re-order the digital data is referred to as “bitslip.”
For some networking and telecommunication standards, a “training pattern” is used to initialize a link. The training pattern is a repetitive pattern that is sent that allows a receiver to achieve “data alignment” and “lane alignment”. The exact same training pattern is sent across all “lanes”. A lane is defined as a single data line from the transmitter to the receiver. The data line can be single ended or differential. The exact number of data lines is dependent on the implementation. Generally, the number of data lines is a multiple of two.
Data alignment is the process where each individual receiver on a data line aligns the data that is received to the forwarded clock. For example, a receiver may use a delay element to center the data in the middle of the forwarded clock. This process allows the receiver to know that it is taking in valid data. Each receiver works independently from the other receivers. Once data alignment has been achieved, the lane alignment begins.
Lane alignment uses a bitslip function along with the training pattern. For example, suppose a training pattern is the six-character sequence of ABCDEF, where ABCDEF represent a sequence of 6 binary digits. Lane alignment is the procedure where each individual lane aligns its output so that an output sequence of ABCDEF is obtained from each such lane. If a receiver does not output the sequence of ABCDEF, the bitslip function is used to “shift” the pattern output until the training pattern, in this example ABCDEF, is obtained. In this example, there are six possible combinations of ABCDEF that a receiver may receive, where each bit is the first of a sequence (e.g., DEFABC). Using the bitslip function enough times, lane alignment is achieved when the output pattern is the training pattern, which in this example is ABCDEF.
A receiver may receive data in serial and provide data in parallel. However, output of such parallel data is to conform to the training sequence. A conventional bitslip circuit converts the parallel data to serial data with induced clock latency, and then reorders (“bitslips”) the converted serial data.
Accordingly, it would be desirable and useful to provide a bitslip circuit capable of directly reordering parallel data.